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CY28341
Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
Features
* Supports VIA P4M266/KM266 chipsets Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1100 1111 CPU 66.80 100.00 120.00 133.33 72.00 105.00 160.00 140.00 77.00 110.00 180.00 150.00 90.00 100.00 200.00 133.33 AGP 66.80 66.80 60.00 66.67 72.00 70.00 64.00 70.00 77.00 73.33 60.00 60.00 60.00 66.67 66.67 66.67 PCI 33.40 33.40 30.00 33.33 36.00 35.00 32.00 35.00 38.50 36.67 30.00 30.00 30.00 33.33 33.33 33.33 * Supports Pentium(R) 4, AthlonTM processors * Supports two DDR DIMMS * Supports three SDRAMS DIMMS at 100 MHz * Provides: -- Two different programmable CPU clock pairs -- Six differential SDRAM DDR pairs -- Three low-skew/low-jitter AGP clocks -- Seven low-skew/low-jitter PCI clocks -- One 48M output for USB -- One programmable 24M or 48M for SIO * Dial-a-FrequencyTM and Dial-a-dB features * Spread Spectrum for best electromagnetic interference (EMI) reduction * Watchdog feature for systems recovery * SMBus-compatible for programmability * 56-pin SSOP and TSSOP packages
Block Diagram
XIN XOUT XTAL REF0 VDDR REF(0:1) VDDI CPUCS_T/C
FS0
Pin Configuration[1]
*FS0/REF0 VSSR XIN XOUT VDDAGP AGP0 *SELP4_K7/AGP1 AGP2 VSSAGP **FS1/PCI_F **SELSDR_DDR/PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 PCI6 VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD#/SRESET# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VTTPWRGD#/REF1 VDDR VSSC CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_C CPUCS_T VSSI FBOUT BUF_IN DDRT0/SDRAM0 DDRC0/SDRAM1 DDRT1/SDRAM2 DDRC1/SDRAM3 VDDD VSSD DDRT2/SDRAM4 DDRC2/SDRAM5 DDRT3/SDRAM6 DDRC3/SDRAM7 VDDD VSSD DDRT4/SDRAM8 DDRC4/SDRAM9 DDRT5/SDRAM10 DDRC5/SDRAM11
SELP4_K7#
VDDC CPU(0:1)/CPU0D_T/C VDDPCI
FS2
PLL1 FS3 FS1
PCI(3:6) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:2) VDD48M 48M
/2
PD#
SDATA SCLK
SMBus
PLL2 WDEN
24_48M
WD SELSDR_DDR Buf_IN S2D CONVERT
SRESET# VDDD FBOUT DDRT(0:5)/SDRAM(0,2,4,6,8,10) DDRC(0:5)/SDRAM(1,3,5,7,9,11)
56 pin SSOP
Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
C Y 28341
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www.SpectraLinear.com
CY28341
Pin Description[2]
Pin 3 4 1 XIN XOUT FS0/REF0 VDD VDD Name PWR I/O I O Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN.
I/O Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When PU the power supply voltage crosses the input threshold voltage, FS0 state is latched and this pin becomes REF0, buffered copy of signal applied at XIN. I If SELP4_K7 = 1, with a P4 processor setup as CPUT/C. At power-up, VTT_PWRGD# is an input. When this input transitions to a logic LOW, the FS (3:0) and MULTSEL are latched and all output clocks are enabled. After the first HIGH to LOW transition on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the device thereafter. When the VTT_PWRGD# feature is not used, please connect this signal to ground through a 10K resistor. If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C). VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes REF1 and is a buffered copy of the signal applied at XIN. These pins are programmable through strapping pin11, SELSDR_DDR#.If SELSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are "True" copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for SDRAM(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V These pins are programmable through strapping pin11, SELSDR_DDR#.If SelSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are "Complementary" copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for SDRAM(1,3,5,7,9,11) single-ended clock outputs, copies of (and in phase with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V.
56
VTTPWRGD#
VDDR
REF1
VDDR
O
44,42,38, DDRT VDDD 36,32,30 (0:5)/SDRAM(0,2,4,6, 8,10)
O
VDDD 43,41,37 DDRC 35,31,29 (0:5)/SDRAM(1,3,5,7, 9,11)
O
7
SELP4_K7 / AGP1
VDDAG P
I/O Power-on Bidirectional Input/Output. At power-up, SELP4_K7 is the input. PU When the power supply voltage crosses the input threshold voltage, SELP4_K7 state is latched and this pin becomes AGP1 clock output. SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode. I/O Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. PU When the power supply voltage crosses the input threshold voltage, MULTSEL state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x IREFMULTSEL = 1, Ioh is 6 x IREF. O 3.3V CPU Clock outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock Output. See Table 1. 3.3V CPU Clock outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock Output. See Table 1. 2.5V CPU Clock Outputs for Chipset. See Table 1. PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1.
12
MULTSEL / PCI2
VDDPCI
53
CPUT/CPUOD_T
VDDC
52
CPUC/CPUOD_C
VDDC
O
48,49
CPUCS_T/C
VDDI VDDPCI VDDPCI
O O
14,15,17, PCI (3:6) 18 10 FS1/PCI_F
I/O Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When PD the power supply voltage crosses the input threshold voltage, FS1 state is latched and this pin becomes PCI_F clock output. I/O Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When PD the power supply voltage crosses the input threshold voltage, FS3 state is latched and this pin becomes 48M, a USB clock output.
20
FS3/48M
VDD48M
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Pin Description[2] (continued)
Pin 11 Name PWR I/O Description SELSDR_DDR#/PCI VDDPCI 1 I/O Power-on Bidirectional Input/Output. At power-up, SELSDR_DDR is the PD input. When the power supply voltage crosses the input threshold voltage, SELSDR_DDR state is latched and this pin becomes PCI clock output.SelSDR_DDR#. = 0, DDR Mode. SelSDR_DDR#. = 1, SDR Mode. I/O Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When PD the power supply voltage crosses the input threshold voltage, FS2 state is latched and this pin becomes 24_48M, a SIO programmable clock output. O O I AGP Clock Output. Is synchronous to CPU clocks. See Table 1. AGP Clock Output. Is synchronous to CPU clocks. See Table 1. Current reference programming input for CPU buffers. A precise resistor is attached to this pin, which is connected to the internal current reference.
21
FS2/24_48M
VDD48M
6 8 25 28
AGP0 AGP2 IREF SDATA
VDDAG P VDDAG P
I/O Serial Data Input. Conforms to the Philips I2C specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. I Serial Clock Input. Conforms to the Philips I2C specification. I/O Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0, this pin PU becomes a SRESET# open drain output, and the internal pulled up is not active. See system reset description. If Byte6 Bit7 = 1 (default), this pin becomes PD# input with an internal pull-up. When PD# is asserted LOW, the device enters power-down mode. See power management function. If SelSDR_DDR#.= 0, 2.5V CMOS type input to the DDR differential buffers.If SelSDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer. If SelSDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the signal applied at BUF_IN. It is in phase with the DDRT(0:5) signals.If SelSDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal applied at BUF_IN. It is in phase with the SDRAM(0:11) signals 3.3V Power Supply for AGP clocks 3.3V Power Supply for CPUT/C clocks 3.3V Power Supply for PCI clocks 3.3V Power Supply for REF clock 2.5V Power Supply for CPUCS_T/C clocks 3.3V Power Supply for 48M 3.3V Common Power Supply If SelSDR_DDR#.= 0, 2.5V Power Supply for DDR clocksIf SelSDR_DDR#.= 1, 3.3V Power Supply for SDR clocks. Ground for AGP clocks Ground for PCI clocks Ground for CPUT/C clocks Ground for DDR clocks Ground for 48M clock Ground for ICPUCS_T/C clocks Common Ground
27 26
SCLK PD#/SRESET#
45 46
BUF_IN FBOUT
5 51 16 55 50 22 23 34,40 9 13 54 33,39 19 47 24
VDDAGP VDDC VDDPCI VDDR VDDI VDD48M VDD VDDD VSSAGP VSSPCI VSSC VSSD VSS48M VSSI VSS
Note: 2. PU = internal Pull-up. PD = internal Pull-down. Typically = 250 kW (range 200 kW to 500 kW).
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Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2. Command Code Definition Bit 7 (6:0) 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be "0000000" Description Data Protocol The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The Block Write and Block Read protocol is outlined in Table 3, while Table 4 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit "00000000" stands for Block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit "00000000" stands for Block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
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Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits "1xxxxxxx" stands for byte operationbit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 Byte Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits "1xxxxxxx" stands for byte operationbit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Serial Control Registers
Byte 0: Frequency Select Register Bit 7 6 5 4 3 @Pup 0 H/W Setting H/W Setting H/W Setting 0 21 10 1 Pin# Name Reserved FS2 FS1 FS0 Reserved For Selecting Frequencies see Table 1. For Selecting Frequencies see Table 1. For Selecting Frequencies see Table 1. If this bit is programmed to "1," it enables Write to bits (6:4,1) for selecting the frequency via software (SMBus). If this bit is programmed to a "0," it enables only Read of bits (6:4,1), which reflects the hardware setting of FS(0:3). 11 20 7 SELSDR_DDR Only for reading the hardware setting of the SDRAM interface mode, status of SELSDR_DDR# strapping. FS3 SELP4_K7 For Selecting frequencies see Table 1 Only for reading the hardware setting of the CPU interface mode, status of SELP4_K7# strapping. Description
2 1 0
H/W Setting H/W Setting H/W Setting
Byte 1: CPU Clocks Register Bit 7 6 5 4 3 2 @Pup 0 1 1 1 1 1 48,49 53,52 Pin# Name MODE SSCG SST1 SST0 CPUCS_T, CPUCS_C CPUT/CPUOD_T CPUC/CPUOD_C Description 0 = Down Spread. 1 = Center Spread. See Table 9. 1 = Enable (default). 0 = Disable Select spread bandwidth. See Table 9. Select spread bandwidth. See Table 9. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disable.
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Byte 1: CPU Clocks Register (continued) 1 1 53,52 CPUT/C In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW, CPUT stops in a HIGH state, CPUC stops in a LOW state. In P4 mode, 1 = when PD# asserted LOW, CPUT and CPUC stop in High-Z. Only For reading the hardware setting of the Pin11 MULT0 value.
0
1
11
MULT0
Byte 2: PCI Clock Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 10 18 17 15 14 12 11 Pin# Name PCI_DRV PCI_F PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Description PCI clock output drive strength 0 = Normal, 1 = increase the drive strength 20%. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
Byte 3: AGP/Peripheral Clocks Register Bit @Pup 7 6 5 4 3 2 1 0 0 1 1 0 0 1 1 1 Pin# 21 20 21 6,7,8 6,7,8 8 7 6 Name 24_48M 48MHz 24_48M DASAG1 DASAG0 AGP2 AGP1 AGP0 Description "0" = pin21 output is 24MHz. Writing a "1" into this register asynchronously changes the frequency at pin21 to 48 MHz. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. Programming these bits allow shifting skew of the AGP(0:2) signals relative to their default value. See Table 5. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
Table 5. Dial-a-SkewTM AGP(0:2) DASAG (1:0) 00 01 10 11 Byte 4: Peripheral Clocks Register Bit @Pup Pin# 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 1 20 21 6,7,8 6,7,8 1 56 1 56 Name 48M 24_48M 1 = normal strength, 0 = high strength 1 = normal strength, 0 = high strength 1 = normal strength, 0 = high strength 1 = normal strength, 0 = high strength Description AGP(0:2) Skew Shift Default -280 ps +280 ps +480 ps
DARAG1 Programming these bits allow modifying the frequency ratio of the AGP(2:0), PCI(6:1, F) clocks DARAG0 relative to the CPU clocks. See Table 6. REF0 REF1 REF0 REF1 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. (K7 Mode only.) 1 = normal strength, 0 = high strength 1 = normal strength, 0 = high strength (K7 Mode only.)
Table 6. Dial-A-RatioTM AGP(0:2) DARAG (1:0) CU/AGP Ratio
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CY28341
Table 6. Dial-A-RatioTM AGP(0:2) 00 01 10 11 Byte 5: SDR/DDR Clock Register Bit 7 @Pup 0 Pin# 45 Name BUF_IN threshold voltage FBOUT Description DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05VSDR Mode, BUF_IN threshold setting. 0 = 1.35V, 1 = 1.25V 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. Frequency Selection Default 2/1 2.5/1 3/1
6 5 4 3 2 1 0
1 1 1 1 1 1 1
46 29,30 31,32 35,36 37,38 41,42 43,44
DDRT/C5/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. RAM(10,11) DDRT/C4/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. RAM(8,9) DDRT/C3/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. RAM(6,7) DDRT/C2/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. RAM(4,5) DDRT/C1/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. RAM(2,3) DDRT/C0/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. RAM(0,1)
Byte 6: Watchdog Register Bit @Pup Pin# 7 6 1 0 26 Name Description SRESET# 1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET# signal. Frequency This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time Revert out only.0 = selects frequency of existing H/W setting1 = selects frequency of the second to last S/W setting (the software setting prior to the one that caused a system reboot). WDTEST WD-Test, ALWAYS program to "0." WD Alarm This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). WD3 WD2 WD1 WD0 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7. This bit allows the selection of the time stamp for the Watchdog timer. See Table 7. This bit allows the selection of the time stamp for the Watchdog timer. See Table 7. This bit allows the selection of the time stamp for the Watchdog timer. See Table 7.
5 4 3 2 1 0
0 0 0 0 0 0
Table 7. Watchdog Time Stamp WD3 0 0 0 0 0 0 0 0 1 1 1 WD2 0 0 0 0 1 1 1 1 0 0 0 WD1 0 0 1 1 0 0 1 1 0 0 1 WD0 0 1 0 1 0 1 0 1 0 1 0 Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds FUNCTION
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Table 7. Watchdog Time Stamp 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds
Byte 7: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Name Reserved N6, MSB N5 N4 N3 N2 N3 N0, LSB Description Reserved for device function test. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock.
Byte 8: Silicon Signature Register (All bits are Read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Pin# Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vender_ID3 Vender_ID2 Vender_ID1 Vender_ID0 Revision ID bit [3] Revision ID bit [2] Revision ID bit [1] Revision ID bit [0] Cypress Vender ID bit [3]. Cypress Vender ID bit [2]. Cypress Vender ID bit [1]. Cypress Vender ID bit [0]. Description
Byte9: Dial-A-Frequency Control Register R Bit @Pup 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R5, MSB R4 R3 R2 R1 R0 DAF_ENB This Edge-trigger bit enables the Dial-a-Frequency N and R bits. It is the transition of this bit from "0" to "1" that latches the N(6:0) and R(5:0) data into the internal N and R registers. The user must only program a one time "1" into this bit for every new N and R values Table 8. FS(4:0) XXXXX P 96016000 Pin# Name Reserved These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via Byte7 and Byte9. P is a PLL constant that depends on the frequency selection prior to accessing the Dial-a-Frequency feature.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 7.
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Table 9. Spread Spectrum Table Mode 0 0 0 0 1 1 1 1 SST1 0 0 1 1 0 0 1 1 SST0 0 1 0 1 0 1 0 1 % Spread -1.5% -1.0% -0.7% -0.5% 0.75% 0.5% 0.35% 0.25% operation of the system in case of a hang-up due to the frequency change. When the system sends an SMBus command requesting a frequency change through Byte 4 or through Bytes 13 and 14, it must have previously sent a command to Byte 12, for selecting which time out stamp the Watchdog must perform, otherwise the System Self Recovery feature will not be applicable. Consequently, this device will change frequency and then the Watchdog timer starts timing. Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in Byte 12,Bits (3:0) (reprogram to 0000), before the Watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. If the Watchdog times out the first time before the new SMBus reprograms Byte12,Bits (3:0) to (0000), then this device will send a low system reset pulse, on SRESET# (see Byte12,Bit7), and changes WD alarm (Byte12,Bit4) status to "1" then restarts the Watchdog timer again. If the Watchdog times out a second time, then this device will send another low pulse on SRESET#, will relatch original hardware strapping frequency (or second to last software selected frequency, see Byte12,Bit6) selection, set WD alarm bit (Byte12,Bit4) to "1," then start WD timer again. The above-described sequence will keep repeating until the BIOS clears the SMBus Byte12,Bits(3:0). Once the BIOS sets Byte12,Bits(3:0) = 0000, then the Watchdog timer is turned off and the WD alarm bit (Byte12,Bit4) is reset to"0."
S y s te m r u n n in g w ith o r ig in a lly s e le c t e d f r e q u e n c y v ia h a r d w a r e s t r a p p in g .
Swing Select Functions Through Hardware
MULT- Board Target Reference R, Output SEL Trace/Term Z IREF = VDD/(3*Rr) Current VOH@Z 0 1 50 Ohm 50 Ohm Rr = 221 1%, IOH = 4 * 1.0V@50 IREF = 5.00 mA Iref Rr = 475 1%, IOH = 6 * 0.7V@50 IREF = 2.32 mA Iref
System Self-recovery Clock Management
This feature is designed to allow the system designer to change frequency while the system is running and reboot the
No F r e q u e n c y w ill c h a n g e b u t S y s t e m S e lf R e c o v e r y n o t a p p lic a b le ( n o t im e s t a m p s e le c t e d a n d b y t e 1 2 , b it ( 3 : 0 ) is s t ill = "0 0 0 0 " R e c e iv e F r e q u e n c y C h a n g e R e q u e s t v ia S M B u s B y t e 4 o r V ia D ia la -fre q u e n c y ? Yes
No I s S M B u s B y t e 9 , t im e o u t s t a m p e n a b le d - ( b y t e 1 2 , b it (3 :0 ) 0 0 0 0 )?
C h a n g e to a n e w fre q u e n c y
1 ) S e n d a n o t h e r 3 m S lo w p u ls e o n S 2 ) R e la t c h o r ig in a l h a r d w a r e s t r a p p in f o r r e t u r n t o o r ig in a l f r e q u e n c y s e t t in g 3 ) S e t W D A la r m b it ( b y t e 1 2 , B it 4 ) t o 4 ) S ta r t W D tim e r Yes
RESET g s e le c tio n s. "1 "
Yes S ta r t in te r n a l w a tc h d o g tim e r .
W a t c h D o g t im e o u t ?
1) Send SR ESET p u ls e 2 ) S e t W D b it ( b y t e 1 2 , b it 4 ) t o '1 ' 3 ) S t a r t W D t im e r
Yes
W a tc h D o g tim e o u t?
No
No S M B u s b y te 1 2 tim e o u t s t a m p d is a b le d ? S M B u s b y te 9 tim e o u t s t a m p d is a b le d , B y t e 1 2 , b it( 3 :0 ) = ( 0 0 0 0 ) ? Yes Yes T u r n o f f w a t c h d o g t im e r . K e e p n e w fr e q u e n c y s e ttin g . S e t W D b it ( b y t e 1 2 , b it 4 ) t o ''0 ' No
No
a la r m
Figure 1.
Power Management Functions
All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks are stopped in the LOW state. All clocks maintain a valid HIGH period on transitions from running to stop and on transitions from stopped to running when the chip was not powered down. On power-up, the VCOs will stabilize to the correct pulse widths within about 0.5 mS.
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CY28341
Maximum Ratings[3]
Input Voltage Relative to VSS:...............................VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................ -65 C to + 150 C Operating Temperature:.................................... 0 C to +70 C Maximum ESD............................................................. 2000V This device contains circuitry to protect inputs against damage due to high-static voltages or electric field. However, precautions should be take to avoid application of any voltage higher than the maximum-rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: VSS < (VIN or VOUT) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
Maximum Power Supply: ................................................ 5.5V DC Parameters VDD = VDDPCI = VDDAGP = VDDR = VDD48M = VDDC = 3.3V 5%, VDDI = VDD = 2.5V 5%, TA = 0C to +70C Parameter VIL1 VIH1 VIL2 VIH2 Vol Iol Ioz Idd3.3V Idd2.5V Ipd Ipup Ipdwn Cin Cout Lpin Cxtal Description Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage for SRESET# Pull-down Current for SRESET# Three-state Leakage Current Dynamic Supply Current Dynamic Supply Current Power-down Supply Current Internal Pull-up Device Current Internal Pull-down Device Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Conditions Applicable to PD#, F S(0:4) Applicable to SDATA and SCLK IOL VOL = 0.4V CPU Frequency Set at 133.3 MHz[5] CPU Frequency Set at 133.3 MHz[5] PD# = 0 Input @ VSS Input @ VDD 2.2 0.4 24 Min. 2.0 1.0 Typ. Max. 0.8 Unit Vdc Vdc Vdc Vdc V mA A mA mA A A A pF pF pF pF
35 150 175 95 10 190 195 600 -25 10 5 6 7 45
Measured from the XIN or XOUT to VSS
27
36
AC Parameters
100 MHz Parameter XTAL TDC TPeriod VHIGH VLOW Tr/Tf TCCJ Txs TDC TPeriod Tr/Tf Description XIN Duty Cycle XIN Period XIN High Voltage XIN Low Voltage XIN Rise and Fall Times XIN Cycle to Cycle Jitter Crystal Start-up Time CPUT/C Duty Cycle CPUT/C Period CPUT/C Rise and Fall Times Rise/Fall Matching Delta Tr/Tf Rise/Fall Time Variation 45 9.85 175 Min. 45 69.841 0.7VDD 0 Max. 55 71.0 VDD 0.3VDD 10.0 500 30 55 10.2 700 20% 125 45 7.35 175 133MHz Min. 45 69.84 0.7VDD 0 Max 55 71.0 VDD 0.3VDD 10 500 30 55 7.65 700 20% 125 45 4.85 175 200 MHz Min. 45 69.84 0.7VDD 0 Max 55 71.0 VDD 0.3VDD 10 500 30 55 5.1 700 20% 125 ps Unit % ns V V ns ps ms % ns ps Notes[4] 7,8 7,8 9 10 10 11,12 12,9 7,11,14,21, 22 7,11,14,21, 22 23,24 23,26,24 11,23,22
P4 Mode CPU at 0.7V
Notes: 3. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. All notes for this table may be found at the end of the table, on page 13.
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AC Parameters (continued)
100 MHz Parameter TSKEW TCCJ Vcross Description CPUCS_T/C to CPUT/C Clock Skew CPUT/C Cycle to Cycle Jitter Crossing Point Voltage at 0.7V Swing Min. 0 -150 280 Max. 200 +150 430 0 -150 280 133MHz Min. Max 150 +150 430 200 MHz Min. 0 -200 280 Max 200 +200 430 Unit ps ps mV Notes[4] 11,15,21,22 11,15,21,22 22
P4 Mode CPU at 1.0V TDC CPUT/C Duty Cycle TPeriod CPUT/C Period Differential CPUT/C Rise and Fall Times Tr/Tf TSKEW TCCJ Vcross SEDeltaSlew K7 Mode TDC TPeriod TLOW Tf TSKEW TCCJ VD VX CPUCS_T/C to CPUT/C Clock Skew CPUT/C Cycle to Cycle Jitter Crossing Point Voltage at 1V Swing Absolute Single-ended Rise/Fall Waveform Symmetry CPUOD_T/C Duty Cycle CPUOD_T/C Period CPUOD_T/C LOW Time CPUOD_T/C Fall Time CPUCS_T/C to CPUT/C Clock Skew CPUOD_T/C Cycle to Cycle Jitter Differential Voltage AC Differential Crossover Voltage
45 9.85 175 0 -150 510
55 10.2 467 200 +150 760 325
45 7.35 175 0 -150 510
55 7.65 467 150 +150 760 325
45 4.85 175 0 -200 510
55 5.1 467 200 +200 760 325
% nS ps 0 ps mV ps
11,14,21 11,14,21 13,15,25 11,15,21 11,15,21 26 24,31
45 9.98 2.8 0.4 0 -150 0.4 500 45 10.0 0.4 0.4
55 10.5 1.6 200 +150 Vp+.6V 1100 55 10.5 1.6 Vp+.6V
45 7.5 1.67 0.4 0 -150 0.4 500 45 15 0.4 0.4
55 8.0 1.6 150 +150 Vp+.6V 1100 55 15.5 1.6 Vp+.6V
45 5 2.8 0.4 0 -200 0.4 500 45 10.0 0.4 0.4
55 5.5 1.6 200 +200 Vp+.6V 1100 55 10.5 1.6 Vp+.6V
% ns ns ns 0 ps V mV % ns ns V V
11,14 11,14 11,14 11,13 11,15,21 11,14 20 19 7,11,14 7,11,14 7,11,13 27 21
CHIPSET CLOCK TDC CPUCS_T/C Duty Cycle TPeriod Tr / Tf VD VX AGP TDC TPeriod THIGH TLOW Tr / Tf TSKEW TCCJ PCI TDC TPeriod CPUCS_T/C Period CPUCS_T/C Rise and Fall Times Differential Voltage AC Differential Crossover Voltage
0.5*VDDI 0.5*VDDI + 0.5*VDDI 0.5*VDDI 0.5*VDDI 0.5*VDDI - 0.2 - 0.2 - 0.2 0.2 + 0.2 + 0.2 45 15 5.25 5.05 0.4 1.6 250 500 45 30.0 55 45 30.0 55 16 45 15 5.25 5.05 0.4 1.6 250 500 55 45 30.0 55 16 45 15 5.25 5.05 0.4 1.6 250 500 55 55 16
AGP(0:2) Duty Cycle AGP(0:2) Period AGP(0:2) HIGH Time AGP(0:2) LOW Time AGP(0:2) Rise and Fall Times Any AGP to Any AGP clock Skew AGP(0:2) Cycle to Cycle Jitter PCI(_F,1:6) Duty Cycle PCI(_F,1:6) Period
% ns ns ns ns ps ps % ns
7,11,14 7,11,14 11,16 11,17 11,13 11,15 11,14,15 7,11,14 7,11,14
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CY28341
AC Parameters (continued)
100 MHz Parameter THIGH TLOW Tr / Tf TSKEW TCCJ 48MHz TDC TPeriod Tr / Tf TCCJ 24MHz TDC TPeriod Tr / Tf TCCJ REF TDC TPeriod Tr / Tf TCCJ DDR VX VD TDC TPeriod Tr / Tf TSKEW TCCJ THPJ TDelay TSKEW tstable Description PCI(_F,1:6) HIGH Time PCI(_F,1:6) LOW Time PCI(_F,1:6) Rise and Fall Times Any PCI to Any PCI Clock Skew PCI(_F,1:6) Cycle to Cycle Jitter 48MHz Duty Cycle 48MHz Period 48MHz Rise and Fall Times 48MHz Cycle to Cycle Jitter 24MHz Duty Cycle 24MHz Period 24MHz Rise and Fall Times 24MHz Cycle to Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter Crossing Point Voltage of DDRT/C Differential Voltage Swing DDRT/C(0:5) Duty Cycle DDRT/C(0:5) Period DDRT/C(0:5) Rise/Fall Slew Rate DDRT/C to Any DDRT/C Clock Skew DDRT/C(0:5) Cycle to Cycle Jitter DDRT/C(0:5) Half-period Jitter BUF_IN to Any DDRT/C Delay FBOUT to Any DDRT/CSkew All Clock Stabilization from Power-up 1 45 69.8413 1.0 45 41.660 1.0 45 20.8299 1.0 Min. 12.0 12.0 0.5 2.5 500 500 55 20.8333 4.0 500 55 41.667 4.0 500 55 71.0 4.0 1000 45 69.8413 1.0 45 41.660 1.0 45 1.0 Max. 133MHz Min. 12.0 12.0 0.5 2.5 500 500 55 4.0 500 55 41.667 4.0 500 55 71.0 4.0 1000 45 69.8413 1.0 45 41.660 1.0 45 1.0 Max 200 MHz Min. 12.0 12.0 0.5 2.5 500 500 55 4.0 500 55 41.667 4.0 500 55 71.0 4.0 1000 Max Unit ns ns ns ps ps % ns ns ps % ns ns ps % ns ns ps V V % ns V/ns ps ps ps ns ps ms Notes[4] 11,16 11,17 11,13 11,15 11,14,15 7,11,14 7,11,14 11,13 11,14,15 7,11,14 7,11,14 11,13 11,14,15 7,11,14 7,11,14 11,13 11,14,15 19 20 21 21 13 11,15,21 11,15,21 11,15,21 11,14 11,14 18
20.8299 20.8333 20.8299 20.8333
0.5*VDD 0.5*VDDD + 0.5*VDD 0.5*VDD 0.5*VDD 0.5*VDD - 0.2 0.2 D - 0.2 D+ 0.2 D-0.2 D+0.2 0.7 45 9.85 1 VDDD + 0.6 55 10.2 3 100 75 100 4 100 3 1 0.7 45 14.85 1 VDDD + 0.6 55 15.3 3 100 75 100 4 100 3 1 0.7 45 9.85 1 VDDD + 0.6 55 10.2 3 100 75 100 4 100 3
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CY28341
AC Parameters (continued)
100 MHz Parameter Description Min. Max. 133MHz Min. Max 200 MHz Min. Max Unit Notes[4]
Notes: 5. All outputs loaded as per maximum capacitive load table. 6. All outputs are not loaded. 7. This parameter is measured as an average over a 1- s duration, with a crystal center frequency of 14.31818 MHz. 8. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 9. When crystal meets minimum 40-ohm device series resistance specification. 10. Measured between 0.2VDD and 0.7VDD. 11. All outputs loaded as per loading specified in the Table 11. 12. When XIN is driven from an external clock source (3.3V parameters apply). 13. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and between 20% and 80% for differential signals. 14. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals. 15. This measurement is applicable with Spread ON or spread OFF. 16. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals) 17. Probes are placed on the pins, and measurements are acquired at 0.4V. 18. The time specified is measured from when all VDD's reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the specifications. 19. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same. 20. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary DDRC (and CPUCS_C) one. 21. Measured at VX, or where subtraction of CLK-CLK# crosses 0 volts. 22. See Figure 10. for 0.7V loading specification. 23. Measured from Vol=0.175V to Voh=0.525V. 24. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as "the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time". This parameter is designed for waveform symmetry. 25. Measurement taken from differential waveform, from -0.35V to +0.35V. 26. Measured in absolute voltage, i.e. single-ended measurement. 27. Measured at VX between the rising edge and the following falling edge of the signal. 28. Measured at VX between the falling edge and the following rising edge of the signal. 29. This parameter is intended to be 0.45*Tperiod(min) for minimum spec. and 0.55*Tperiod(min) for maximum spec. 30. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).
P4 Processor SELP4_K7# = 1 Power-down Assertion (P4 Mode) When PD# is sampled LOW by two consecutive rising edges of CPU# clock then all clock outputs except CPU clocks must be held LOW on their next HIGH to LOW transition. CPU clocks must be held with the CPU clock pin driven HIGH with a value of 2 x Iref, and CPU# undriven. Note that Figure 4
PW RDW N# C PU T 133M H z C PU T# 133M H z PC I 33M H z AG P 66M H z U SB 48M H z R E F 1 4 .3 1 8 M H z D D R T 133M H z D D R C 133M H z SD R AM 133M H z
shows CPU = 133 MHz, this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Figure 2. Power-down Assertion Timing Waveform (in P4 Mode)
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CY28341
Power-down Deassertion (P4 Mode) The power-up latency needs to be less than 3 mS.
< 1 .5 m s e c PW RDW N# CPU 133M Hz CPU# 133M Hz PCI 33M Hz AG P 66M Hz USB 48M Hz R E F 1 4 .3 1 8 M H z DDRT 133M Hz DDRC 133M Hz SDRAM 133M Hz
Figure 3. Power-down Deassertion Timing Waveform (in P4 Mode)
AMD K7 Processor SELP4_K7# = 0
Power-down Assertion (K7 Mode) When the PD# signal is asserted LOW, all clocks are disabled to a LOW level in an orderly fashion prior to removing power from the part. When PD# is asserted (forced) LOW, the device transitions to a shutdown (power-down) mode and all power supplies may then be removed. When PD# is sampled LOW
PW RDW N# C PUO D_T 133M Hz C PU CS_T 133M Hz C PU O D _C 133M Hz CPUC S_C 133M Hz PCI 33M Hz AG P 66M Hz U SB 48M Hz R E F 1 4 .3 1 8 M H z DD RT 133M Hz DDR C 133M Hz SD RAM 133M Hz
by two consecutive rising edges of CPU clock, then all affected clocks are stopped in a LOW state as soon as possible. When in power-down (and before power is removed), all outputs are synchronously stopped in a LOW state (see figure3 below), all PLL's are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I2C function is also disabled.
Figure 4. Power-down Assertion Timing Waveform (in K7 Mode)
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CY28341
Power-down Deassertion (K7 Mode) When de-asserted PD# to HIGH level, all clocks are enabled and start running on the rising edge of the next full period in
< 1 .5 m se c PW RDW N# CPU 133MHz CPU# 133MHz PCI 33MHz AGP 66MHz USB 48MHz R E F 1 4 .3 1 8 M H z DDRT 133MHz DDRC 133MHz SDRAM 133MHz
order to guarantee a glitch-free operation, no partial clock pulses.
Figure 5. Power-down Deassertion Timing Waveform (in K7 mode)
VID (0:3), SEL (0,1) VTT_PW RGD# PW RGD
VDD Clock Gen Clock State State 0
0.2-0.3m S Delay State 1
W ait for VTT_GD#
Sam ple Sels State 2 State 3 (Note A)
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)[31]
Note: 31. This time diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power-up. After the first HIGH to LOW transition of VTT_PWRGD#, device is not affected, VTT_PWRGD# is ignored.
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CY28341
GD WR TP
S1
=L
ow
#
S2
D e la y 0 .2 5 m S
S a m p le In p u ts F S ( 3 :0 )
W a it f o r 1 .1 4 6 m s
VT
E n a b le O u tp u te s
V D D A = 2 .0 V
S0
S3
P o w e r O ff
V D D 3 .3 = O f f
N o rm a l O p e r a tio n
Figure 7. Clock Generator Power-up/ Run State Diagram (with P4 Processor SELP4_K7# = 1)
Connection Circuit DDRT/C Signals
For Open Drain CPU Output Signals (with K7 Processor SELP4_K7# = 0)
3.3V 60.4 Ohm CPUOD_T 47 Ohm Ohm 5" 680 pF 500 Ohm 301 Ohm 47 Ohm CPUOD_C Ohm 5" 680 pF 60.4 Ohm 500 Ohm 3.3V 20 pF VDDCPU(1.5V) Ohm 1" 500 Ohm Ohm " 20 pF VDDCPU(1.5V) 500 Ohm
Measurement Point
Measurement Point
Figure 8.
6"
6"
Figure 9.
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CY28341
Table 10.Signal Loading Table Clock Name REF (0:1), 48MHz (USB), 24_48MHz AGP(0:2), SDRAM (0:11) PCI_F(0:5) DDRT/C (0:5), FBOUT CPUT/C CPUOD_T/C CPUCS_T/C For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1) The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
T PCB CPUT RtA1 MULTSEL CPUT# RtA2 T PCB RLA2 R LB2 RtB2 CLB RLA1 R LB1 RD CLK Measurement Point RtB1 CLA CLK Measurement Point
Max Load (in pF) 20 30 30 See Figure 10 See Figure 8 See Figure 9
Rref
Figure 10. Table 11.Lumped Test Load Configuration Component 0.7V Amplitude Value 1.0V Amplitude Value RtA1, RtA2 RLA1, RLA2 TPCB RLB1, RLB2 RD RtB1, RtB2 CLA, CLB Rref 475 0 2 pF w/mult0 = 1 221 33 49.9 3" 50 Z 3" 50 63 470 33 2 pF w/mult0 = 0 Z 0 tCSAGP CPUCS to AGP tAP AGP to PCI
Group Timing Relationships and Tolerances[32]
Offset (ps) Tolerance (ps) Conditions 750 1,250 500 500 CPUCS Leads AGP Leads
Note: 32. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same length transmission line to the other signal of the pair (e.g., AGP) should be added.
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CY28341
0ns 10ns 20ns 30ns
CPU CLOCK 66.6MHz CPU CLOCK 100MHz CPU CLOCK 133.3MHz tCSAGP AGP CLOCK 66.6MHz tAP PCI CLOCK 33.3MHz
Ordering Information
Part Number CY28341OC CY28341OCT CY28341ZC CY28341ZCT Package Type 56-pin Shrunk Small Outline package (SSOP) 56-pin Shrunk Small Outline package (SSOP)-Tape and Reel 56-pin Thin Shrunk Small Outline package (TSSOP) 56-pin Thin Shrunk Small Outline package (TSSOP)-Tape and Reel Product Flow Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C
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CY28341
Package Drawing and Dimensions
56-lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
56-lead Shrunk Small Outline Package O56
51 85062 C
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
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